X9智舱处理器_X9 Cockpit SoCs_Beijing SemiDrive Technology Corporation

X9 Cockpit SoCs

The X9 series Cockpit SoCs are automobile chips designed by SemiDrive specifically for the new-generation automotive e-cockpit. It integrates high-performance CPUs, GPUs, AI accelerators, and video processors to address the growing demands of new-generation automotive e-cockpit applications for powerful computing capabilities, and rich multimedia performance, etc.

The X9 series products comprehensively cover e-cockpit application scenarios from entry-level to flagship-level, such as virtual cluster, IVI, e-cockpit domain controller, and integrated parking and infotainment system. They have already become the mainstream choice for intelligent automotive e-cockpit chips in China. Currently, there are dozens of high-profile vehicle models with fixed-point installations. Vehicle models equipped with X9 series chips from automakers such as SAIC Motor, Chery Automobile, Changan Automobile, GAC Group, BAIC Group, Dongfeng Nissan, and GAC Honda have all been mass-produced and rolled out on the market.

Product Layout

3D LCD/central control

X9E | X9M | X9H | X9S

10-70 KDMIPS

4-200 GFLOPS

0.2-4 TOPS

16nm Automotive-grade Process
ARMV8.2 CPU.MP2-MP8
1080P cluster / 1080P-2.5K central control
AVM + DMS + DVR
AEC-Q100 Grade 2. IsO26262 ASIL B
Mass production and delivery started in 2021, a full range of products now in mass production

E-cockpit domain controller/integrated parking and infotainment system

X9HP | X9U | X9SP

50-100 KDMIPS

140-300 GFLOPS

0.4-8 TOPS

16nm Automotive-grade Process
ARMv8.2 CPU，Hardware-Independent Architecture
1080P cluster +2.5K central control+HUD
AVM + APA + DMS + OMS + DVR!
AEC-0100 Grade 2 ISO26262 ASIL B
Mass production and delivery started in 2023, a full range of products now in mass production

AI e-cockpit

X10 Series

Automotive-grade Process
ARMv92CPU，硬隔离/虚拟化架构
2K仪表+HUD+4K 中控&副驾
AVM + APA + DMS + OMS + DVR
支持端侧大模型部署，支持Al Agent
AEC Q100 Grade 3.ISO26262 ASIL B

Product Performance

High-performance Processor

Cortex-A55 multi-cluster architecture; High frequency.
Supports multi-screen independent display with high definition and high frame rate.
Supports operating systems such as QNX, Linux, and Android, as well as multiple systems on a single chip.
Efficient resource allocation capability across different domains/cores.

High-performance Built-in AI Unit

Supports deployment of AI applications such as OMS/DMS and speech recognition.
Supports hybrid deployment of large models on cloud and edge, with local multi-modal perception.
Supports algorithms for intelligent driving scenarios (driving/parking).

High Reliability

AEC-Q100 reliability certification.
ASIL B product certification of ISO 26262 for functional safety.
Built-in independent hardware-isolated safety island.
Integrates hardware security module (HSM).

Application Scenarios

Design of product family, with a comprehensive product matrix covering applications such as 3D virtual cluster, IVI, e-cockpit domain controller, integrated parking and infotainment system, integrated parking, driving and infotainment system, and central computing platform etc.
Both hardware Pin-to-Pin compatibility and software compatibility.

Product Family

Device Name	X9E	X9M	X9H	X9S	X9HP	X9SP	X9U
Part Number	X9260	X9480	X9669	X9870	X9699	X9880	X9892
CPU Cluster 1	MP2 @1.6GHz	MP4 @2.0GHz	MP6 @2.0GHz	MP8 @2.3GHz	MP6 @2.0GHz	MP8 @2.3GHz	2 x MP6 @2.0GHz
CPU Cluster 2	-	-	-	-	MP1 @1.4GHz	MP4 @2.0GHz	2 x MP1 @1.4GHz
CPU DMIPS(K)	12	30	45	70	50	100	100K
GPU GFLOPS	40	80	140	230	140	230	300G
NPU	-	-	-	8 TOPS	-	8 TOPS	-
DSP	1 x vDSP	1 x vDSP	1 x vDSP	1 x vDSP	1 x vDSP	2 x vDSP	2 x vDSP
ISP	-	-	-	1Gpixel/s	-	1Gpixel/s/td>	-
DDR LPDDR4/4x	up tp 8GB	up tp 8GB	up tp 8GB	up tp 16GB-	up tp 8GB	up tp 16GB	up tp 16GB
Video H.264	Encoder/Decoder	Encoder/Decoder	Encoder/Decoder	Encoder/Decoder-	Encoder/Decoder	Encoder/Decoder	Encoder/Decoder
Video H.265	Decoder	Decoder	Decoder	Encoder/Decoder	Decoder	Encoder/Decoder	Decoder
FHD Display	2x	3x	4x	4x-	4x	4x	8x
LVD(4-ch)	2x		4x	4x	4x	4x	8x
MIPI DSI(4-Lane)	2x	2x	2x	2x	2x	2x	4x
Parallel CSI	1x	1x	1x	1x	1x	1x	2x
MIPI CSI(4-Lane)	2x	2x	2x	2x	2x	2x	4x
USB3.0	2x	2x	2x	2x	2x	2x	4x
PCle 3.0	1x 1-lane	2x 1-lane	2x 1-lane	2x 1-lane	2x 1-lane	2x 1-lane	2x 1-lane
eMMC	2x eMMC5.1	2x eMMC5.1	2x eMMC5.1	2x eMMC5.1	2x eMMC5.1	2x eMMC5.1	2x eMMC5.1
Ethernet	1x1G Ethernet TSN	1x1G Ethernet TSN	1x1G Ethernet TSN	1x1G Ethernet TSN-	1x1G Ethernet TSN	1x1G Ethernet TSN	2x1G Ethernet TSN
CAN-FD	2x	2x	2x	2x	2x	2x	4x
Multi-Purpose Processor	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	2xR5 DCLS
Secure Processor	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	2xR5 DCLS
Safety Island	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	Cortex-R5 DCLS	2xR5 DCLS
Functional Safety	ASIL B	ASIL B	ASIL B	ASIL B	ASIL B	ASIL B	ASIL B
Auto Grade	AEC-Q100 Grade 2	AEC-Q100 Grade 2	AEC-Q100 Grade 2	AEC-Q100 Grade 2	AEC-Q100 Grade 2	AEC-Q100 Grade 2	AEC-Q100 Grade 2

Note:
Hardware isolation for each CPU Cluster
All the devices except X9U are pin-to-pin and software compatible.

Partners

Solution

App Algorithm

Middleware

Toolchain

BSW

Hardware